Abstract: A method for measuring the coupling rate of the floating-gate voltage in flash memory cells is presented and proved to be feasible. Meanwhile, the degradation of negative gate source-side erased flash memory cells is investigated. Interface states and oxide traps were generated by hot-carrier injection near the source during this erasing process, by which the SILC generated is the major cause for device degradation, on the basis of which, three possible conduction mechanisms are described. he steady-state current and the transient one in the SILC are measured respectively. The conclusion can be drawn from this study that the reliability issue under the action of reading stress is mainly caused by electron tunneling through oxide.

Key words: flash memory, coupling rate, SILC