基于PCIE的多嵌入式人工智能处理器低延迟数据交换技术

doi:10.16180/j.cnki.issn1007-7820.2024.05.005

电子科技 ›› 2024, Vol. 37 ›› Issue (5): 32-37.doi: 10.16180/j.cnki.issn1007-7820.2024.05.005

基于PCIE的多嵌入式人工智能处理器低延迟数据交换技术

魏璇¹^,², 温凯林¹^,³, 李斌², 刘淑涛², 褚洁¹, 蔡觉平¹

1.西安电子科技大学微电子学院,陕西西安 710071
2.中国电子科技集团公司第五十四研究所,河北石家庄 050000
3.苏州鸿鹄骐骥电子科技有限公司,江苏苏州 215000

收稿日期:2022-12-12 出版日期:2024-05-15 发布日期:2024-05-21
作者简介:魏璇(1989-),男,博士研究生,高级工程师。研究方向:高速接口及交换电路。
蔡觉平(1976-),男,博士,教授。研究方向:集成电路设计。
基金资助:
国家自然科学基金(62274123);陕西省重点研发计划重点产业创新链项目(2021ZDLGY02-01)

Multiple Embedded AI Processors Low Latency Data Exchange Technology Based on PCIE Interface

WEI Xuan¹^,², WEN Kailin¹^,³, LI Bin², LIU Shutao², CHU Jie¹, CAI Jueping¹

1. School of Microelectronics,Xidian University,Xi'an 710071,China
2. The 54th Research Institute of China Electronics Technology Group Corporation,Shijiazhuang 050081,China
3. Suzhou Honghu Qiji Electronic Technology Co., Ltd.,Suzhou 215000,China

Received:2022-12-12 Online:2024-05-15 Published:2024-05-21
Supported by:
National Natural Science Foundation of China(62274123);Key Industrial Innovation Chain Project of Shaanxi Key Research and Development Program(2021ZDLGY02-01)

摘要/Abstract

摘要：

针对多嵌入式人工智能(Artificial Intelligence, AI)处理器板卡之间的任务调度和数据交换冲突以及提高多板卡堆叠扩展时的可靠性和运行效率问题,文中提出了一种虫洞交换结构多嵌入式人工智能处理器高速数据交换技术和数据帧结构的解决方法。该方法基于PCIE(PCI Express)高速数据接口,将数据以数据单元的形式进行信息传递,并设计多重权重决策算法避免数据传输中的冲突,实现任务的并发多线程处理。搭建FPGA(Field Programmable Gate Array)平台进行设计和测试,结果表明PCIE的传输带宽利用效率达到了85%以上,数据交换延迟小于20 μs,系统中断任务响应平均最大延迟时间为8.775 μs。该技术适用于多处理器协同的高速交换电路,可扩展至混合PCIE和RapidIO交换电路结构。

关键词: 嵌入式人工智能处理器, 数据交换, 外围组件互连快速, PCI Express, 交换开关, 虫洞技术, 数据仲裁, 多重权重决策

Abstract:

In view of the conflict of task scheduling and data exchange between multiple embedded AI(Artificial Intelligence) processors and improving the reliability and efficiency of stack expansion of multiple AI processors, a high speed data exchange technology and data frame structure of multiple embedded AI processors with wormhole switching structure are proposed in this study. Based on the PCIE(PCI Express) high-speed data interface, the data is transmitted in the form of data unit, and the multi-weight decision algorithm is designed to avoid the conflict in data transmission and realize the concurrent multi-threading of the task.The FPGA(Field Programmable Gate Array) platform is designed and tested. The results show that the transmission bandwidth utilization efficiency of PCIE reaches more than 85%, the data exchange delay is less than 20 μs, and the average maximum delay time of interrupt task response is 8.775 μs.The technology is suitable for high-speed switching circuits with multi-processor collaboration and can be extended to hybrid PCIE and RapidIO switching circuit architectures.

Key words: embedded AI processors, data exchange, fast peripheral component interconnection, PCI Express, exchange switch, wormhole technology, data arbitration, multi-weighted decision making

中图分类号:

TN919

魏璇, 温凯林, 李斌, 刘淑涛, 褚洁, 蔡觉平. 基于PCIE的多嵌入式人工智能处理器低延迟数据交换技术[J]. 电子科技, 2024, 37(5): 32-37.

WEI Xuan, WEN Kailin, LI Bin, LIU Shutao, CHU Jie, CAI Jueping. Multiple Embedded AI Processors Low Latency Data Exchange Technology Based on PCIE Interface[J]. Electronic Science and Technology, 2024, 37(5): 32-37.

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中断向量数目	最小延迟时间/μs	最大延迟时间/μs
1	5.7	6.5
2	5.8	6.5
3	6.2	6.8
4	6.2	7.3
平均延迟时间	6.0	6.8

基于PCIE的多嵌入式人工智能处理器低延迟数据交换技术

Multiple Embedded AI Processors Low Latency Data Exchange Technology Based on PCIE Interface

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