关键词: 模拟乘法器, 动态阈值晶体管, 低压, 低功耗, 金属氧化物半导体

Abstract:

This paper analyses an analog multiplier based on dynamic threshold voltage NMOS transistor for two input transistor.Four dynamic threshold voltage NMOS transistor and two active resistors are used to design a novel 1.2 V low power CMOS analog multiplier.The number of input transistor has been decreased and the biased transistor and circuits have been saved,while the performance is appropriate.The main characteristics are that the margin between the first order harmonious wave and the third order harmonious wave of the output wave is about 40 dB,that the output frequency bandwidth is 375 MHz,and that the average power supply current is 30 μA.The novel analog multiplier can be applied for the design of low power communication integrated circuits.

Key words: analog multiplier;dynamic threshold voltage;low voltage;low power;CMOS