关键词: 抽取滤波器, FPGA, 乘法器

Abstract:

For the implementation of the FIR decimation filter with higher orders,many multipliers are required if the traditional direct or poly phase structure is employed.This increases the implementation difficulty in many practical systems.In this paper,an improved poly phase structure of the decimation filter is designed,which is more suitable for FPGA implementation.In the proposed structure,multi-channels and operations on sum of products are realized with only one multiplier by increasing the clock frequency of the FPGA.In a practical decimation filter system with 4 096-order filter and 512-order decimation ratio,the proposed filter module stably works at a clock frequency of 204.8 MHz and only requires 8 multipliers.

Key words: decimation filter;FPGA;multiplier