关键词: DCM动态重配置, Xilinx Virtex-4, 时钟源

Abstract:

This paper introduces the structure and related characteristics of Digital Clock Manager (DCM) in Xilinx FPGA,proposes a scheme reconfiguring the DCM dynamically based on Xilinx FPGA,and gives the specific implementation system.With just a few external control signal lines connected to Xilinx XC4VFX100,this system can enable DCM to change frequency accurately and quickly between 50 MHz and 300 MHz under the 100 MHz input clock source conditions.This design system features a simple interface,real time and high stability,and has already been applied to some satellite system successfully.

Key words: DCM dynamic reconfiguration ports;Xilinx Virtex-4;clock source