›› 2012, Vol. 25 ›› Issue (6): 110-.

• 论文 • 上一篇    下一篇

通用数字电路板测试系统硬件设计

周博,刘文波   

  1. (南京航空航天大学 自动化学院,江苏 南京 210016)
  • 出版日期:2012-06-15 发布日期:2012-08-23
  • 作者简介:周博(1988—),男,硕士研究生。研究方向:计算机测控。刘文波(1969—),女,教授,博士生导师。研究方向:信号处理及应用,非线性动力系统分析及工程应用,计算机测试与控制技。

Hardware Design of a General Digital Circuit Board Testing System

 ZHOU Bo, LIU Wen-Bo   

  1. (College of Automation Engineering,Nanjing University of Aeronautics and Astronautics,Nanjing 210016,China)
  • Online:2012-06-15 Published:2012-08-23

摘要:

针对传统依靠人工使用示波器、万用表、逻辑分析仪等设备对数字电路板进行测试具有过程复杂、工作量大、可靠性低等缺点,介绍一套通用数字电路板测试系统的硬件设计方案。跟传统数字电路板测试系统相比,文中的设计性能参数更优,主要包括:测试频率最高50 MHz并可调为100 MHz的整数分频;测试电平兼容-6~+9 V且可编程步长为100 mV;测试通道32路,每通道可设为输入输出三态可选且同步工作,存储深度1 Mbit,电流驱动能力达50 mA并有过载保护。

关键词: 数字电路板测试, 嵌入式硬件设计, FPGA

Abstract:

The conventional method of using an oscilloscope,multimeter,logic analyzer or other equipment for digital circuit board testing is complex,time consuming and not reliable.In this paper,the hardware design of a general digital circuit board testing system is introduced.Unlike traditional digital circuit board testing systems,this design has better performance and parameters:the testing frequency can reach 50 MHz and can be set as integer division of 100 MHz;the testing level is compatible to -6 V~+9 V and can be programmed by 100 mV;there are up to 32 channels,each channel having 1 Mbit memory depth and 50 mA current drive capability with overload protection,and can work either as input or output for three-state synchronously.

Key words: digital circuit board testing;embedded hardware design;FPGA

中图分类号: 

  • TN79