SOC芯片的可测试性设计与功耗优化

›› 2012, Vol. 25 ›› Issue (8): 23-.

SOC芯片的可测试性设计与功耗优化

陈志强,林平分,任威丽

(北京工业大学嵌入式系统重点实验室,北京 100022)

出版日期:2012-08-15 发布日期:2012-08-28
作者简介:陈志强(1988—),男,硕士研究生。研究方向:集成电路后端设计与测试。

Design for Testability and Power Optimization in SOC

CHEN Zhi-Qiang, LIN Ping-Fen, REN Wei-Li

(Beijing Embedded System Key Lab,Beijing University of Technology,Beijing 100022,China)

Online:2012-08-15 Published:2012-08-28

摘要/Abstract

摘要：

介绍了数字集成电路可测试性设计与测试覆盖率的概念,针对一款电力网通信芯片完成了可测试性设计,从测试的覆盖率、功耗等方面提出了优化改进方案,切实提高了芯片的测试覆盖率,缩减了测试时间和成本,降低了测试功耗,同时保证了芯片测试的可靠性,最终使芯片顺利通过量产测试。

关键词: 可测试性设计, 低功耗设计, 故障覆盖率

Abstract:

This paper introduces the conception of DFT(Design For Testability) technology and test coverage with a PLC(Power Line Communication) chip as an example.An obvious adjustment has been made based on test coverage and power of the design.These optimization methods have greatly improved test coverage,reduced the cost and power consumption,and improved DFT quality.Finally,the design went on to mass production successfully.

Key words: design for testability(DFT);low power design;test coverage

中图分类号:

TN702

陈志强, 林平分, 任威丽. SOC芯片的可测试性设计与功耗优化[J]. , 2012, 25(8): 23-.

CHEN Zhi-Qiang, LIN Ping-Fen, REN Wei-Li. Design for Testability and Power Optimization in SOC[J]. , 2012, 25(8): 23-.