关键词: QC_LDPC码, 校验矩阵, 分层迭代译码算法, FPGA

Abstract:

This paper proposes a design of regular check matrix for QC_LDPC codes with girth 8 with the side effects of cycles,especially the short cycles,on the performance of LDPC decoders in consideration.The proposed construction algorithm for QC_LDPC codes designs 3 sub matrices with different given shifting functions,then combines them into one matrix,and finally expands the transposed matrix of the combination matrix into a desired parity check matrix using the identity matrix and the cyclic shift matrices of the identity matrix randomly．The layered-decoding algorithm is used for the special structure of check matrix.The design can achieve decoding with 1/2 code rate,3456 code length,and (3,6) regular QC-LDPC codes.The whole design is synthesized under EP3SL340 FPGA of Altera Stratix III.

Key words: QC LDPC codes;check matrix;layered-decoding algorithm;FPGA