关键词: 高速突发通信, 定时同步, 定时控制, Field Programmable Gate Array

Abstract:

This paper discusses a timing synchronization algorithm based on digital squared filtering which applies for burst communication in the case of high-speed data transmission.First,in the case of high speed data transmission,a parallel structure is used to implement the loop of timing error estimation,which greatly reduces the system requirements for the clock and is easier to implement.A comparison between the proposed timing control circuit and those in other papers indicates that the timing control circuit in this paper is better.Finally,the paper provides Matlab simulation and hardware implementation,whose results show that the loop circuit can realize the timing synchronization efficiently in any case.

Key words: high speed burst communication;timing synchronization;timing control;FPGA