一种低相位噪声采样时钟源的设计

›› 2014, Vol. 27 ›› Issue (6): 39-.

一种低相位噪声采样时钟源的设计

蒋小强,石玉,苏安刚,赵宝林

(电子科技大学微电子与固体电子学院,四川成都 610054)

出版日期:2014-06-15 发布日期:2014-06-14
作者简介:蒋小强(1985—),男,硕士研究生。研究方向:射频器件及电路。E-mail:xqj789@126.com

Design of a Sampling Clock with Low Phase Noise

JIANG Xiaoqiang,SHI Yu,SU Angang,ZHAO Baolin

(School of Microelectronics and Solid Electronics,University of Electronic Science and Technology of China,Chengdu 610054,China)

Online:2014-06-15 Published:2014-06-14

摘要/Abstract

摘要：

分析了锁相环频率合成器与数字直接频率合成器的原理,阐述了二者性能的优劣。并在此基础上设计了一款低相位噪声的采样时钟源。该频率源结合锁相环和直接数字频率合成器的优势,在75 MHz时相位噪声可达-119 dBc@1 kHz、-116 dBc@100 kHz。

关键词: 频率源;数字直接频率合成器;滤波器;相位噪声

Abstract:

This paper introduces the theories of phase locked loop and direct digital synthesis,discusses their advantages and disadvantages,and presents the design of a sampling clock with low phase noise using the PLL and DDS technologies.The measurement results show that the phase noise is up to -119 dBc@1 kHz and -116 dBc@100 kHz at 70 MHz.

Key words: phase locked loop;digital direct synthesis;filter;phase noise

中图分类号:

TN74+2.1

蒋小强,石玉,苏安刚,赵宝林. 一种低相位噪声采样时钟源的设计[J]. , 2014, 27(6): 39-.

JIANG Xiaoqiang,SHI Yu,SU Angang,ZHAO Baolin. Design of a Sampling Clock with Low Phase Noise[J]. , 2014, 27(6): 39-.