关键词: 片上网络, FPGA, 边界扫描, 硬件平台

Abstract:

A boundary scan test system is designed with FPGA as the core for fault testing of complex network on chip systems based on 3×3 2D-Mesh structure of NoC system,the boundary scan test technology and the resource node fault types.The frequency meter,amplifier,SRAM,IEEE1500 Wrapper and the boundary scanning chains of resource nodes interface are implemented.The test software,signal generator,AVO meter,digital oscilloscope are used to checkout the whole hardware design through boundary chain.The test results show that the design offers stable performance and provides a hardware platform of boundary scan test in the research of NoC systems.

Key words: network on chip;FPGA;boundary scan;hardware platform