关键词: FPGA, DDR3 SDRAM, MIG, 读写控制器, 状态机

Abstract:

In order to solve the problem of data cache in ultrahigh speed sampling system, a DDR3 SDRAM controller is designed in this paper based on Kintex-7 FPGA MIG_v1.9 IP core. A method to improve the bandwidth utilization ratio is proposed and analyzed. Finally, it is packaged as the FIFO interface, while shielding the complex user interface of DDR3 IP core, so that the DDR3 reading and writing operation can be as simple as FIFOs. System tests show that the proposed method meets the requirements of large capacity data cache, and provides with high portability.

Key words: FPGA;DDR3 SDRAM;MIG;reading writing controller;state machine