基于并行前缀结构的十进制加法器设计

›› 2016, Vol. 29 ›› Issue (6): 19-.

基于并行前缀结构的十进制加法器设计

王书敏崔晓平

(南京航空航天大学电子信息工程学院，江苏南京 211100)

出版日期:2016-06-15 发布日期:2016-06-22
作者简介:王书敏（1990-），男，硕士研究生。研究方向:数字系统设计与计算机应用。崔晓平（1962-），女，副教授，硕士研究生。研究方向：数字系统设计与计算机应用。

Design of Decimal Adder Based on Parallel Prefix Structure

WANG Shumin，CUI Xiaoping

(College of Electronic and Information Engineering, Nanjing University of Aeronautics &Astronautics, Nanjing 210016, China

Online:2016-06-15 Published:2016-06-22

摘要/Abstract

摘要：

针对硬件实现BCD码十进制加法需要处理无效码的问题，设计了一种基于并行前缀结构的十进制加法器。该十进制加法器依据预先加6，配合二进制加法求中间和，然后再减6修正的算法，并将减6修正步骤整合到重新设计的减6修正进位选择加法器中，充分利用并行前缀结构大幅提高了电路运算的并行度。采用Verilog HDL对加法器进行实现并利用Design Compiler进行综合，得到设计的32位，64位，128位的十进制加法器的延时分别为0.56 ns，0.61 ns，0.71 ns，面积分别为1 310 μm2，2 681 μm2，5 485 μm2。

关键词: 十进制加法, 并行前缀结构, 减6修正进位选择加法器

Abstract:

Aiming at the problem that the hardware implementation of the BCD code decimal addition requires the processing of invalid code, a new decimal adder based on the parallel prefix structure is designed. The proposed decimal adder based on the algorithm of adding six to each BCD digit of one operand prior to performing binary addition and then subtract six again if a carryout of the digit is not occur. The parallelism of circuit operation is increased by taking the advantage of parallel prefix structure. The designed decimal adder have been realized by Verilog HDL and synthesized by Design Compiler, the delay of decimal adder in 32 bit, 64 bit and 128 bit is 0.56 ns, 0.61 ns and 0.71 ns; the area is 1310 μm2, 2681 μm2 and 5485 μm2 .

Key words: decimal addition, parallel prefix structure, carry select adder of subtraction 6

中图分类号:

TP332.2

王书敏崔晓平. 基于并行前缀结构的十进制加法器设计[J]. , 2016, 29(6): 19-.

WANG Shumin，CUI Xiaoping. Design of Decimal Adder Based on Parallel Prefix Structure[J]. , 2016, 29(6): 19-.