低功耗SigmaDelta调制器的建模与设计

›› 2016, Vol. 29 ›› Issue (9): 136-.

低功耗SigmaDelta调制器的建模与设计

孔梦华，卜刚，吴振淇

（南京航空航天大学电子信息工程学院，江苏南京 211106）

出版日期:2016-09-15 发布日期:2016-09-26
作者简介:孔梦华（1988-）,男，硕士研究生。研究方向：集成电路设计。吴振淇（1991-）,男，硕士研究生。研究方向：集成电路设计。
基金资助:
江苏省自然科学基金资助项目（BK2012792）

Modeling and Design of the Lowpower SigmaDelta Modulator

KONG Menghua, BU Gang, WU Zhenqi

〗(School of Electronic Information Engineering, Nanjing University of Aeronautics &Astronautics, Nanjing 210016, China)

Online:2016-09-15 Published:2016-09-26

摘要/Abstract

摘要：

针对SigmaDelta ADC在实现高精度的同时如何降低系统功耗这一问题，通过进行建模分析，得出满足精度需求的最低性能指标。并对二阶SigmaDelta调制器的非理想因素进行数学建模分析，在满足ADC精度的同时对ADC组成模块的最低性能指标进行分配，利用SDtoolbox进行仿真验证。基于CSMC 0.5 μmCMOS工艺，在5 V电源电压下，对调制器进行了电路级设计。结果显示在模块最低性能时，调制器输出信号的带内信噪比为835 dB，总功耗为18 mW。

关键词: Sigma Delta调制器, 建模分析, 低功耗设计

Abstract:

The analogtodigital converter (ADC) is the necessary interface for analog signal to digital signal conversion. The minimum performance index of the sigmadelta ADC while meeting the precision demand are obtained by modeling in order to reduce the power consumption of the system while maintaining high precision. The mathematical modeling analysis of the nonideal factors of a secondorder SigmaDelta modulator is performed, and the distribution of minimum performance indicators of the ADC module is simulated with SDtoolbox. Based on 0.5 μm CMOS CSMC process and under the 5 V power supply voltage, this paper presents the modulator circuit design. The results show that the inband signaltonoise ratio is 83.5 dB, and total power consumption is 1.8 mW at minimum performance of the modulator.

Key words: sigma delta modulator, modeling analysis, low power design

中图分类号:

TN761

孔梦华，卜刚，吴振淇. 低功耗SigmaDelta调制器的建模与设计[J]. , 2016, 29(9): 136-.

KONG Menghua, BU Gang, WU Zhenqi. Modeling and Design of the Lowpower SigmaDelta Modulator[J]. , 2016, 29(9): 136-.