关键词: 平板探测器, 模拟前端, 时序, Verilog, 仿真

Abstract:

A method of Verilog realization of the analog front end timing used in the flat panel detector is proposed for the implement with high precision and high speed of analog front end timing. Verilog programming uses of modular design including charge collection module, data reading module and counter module on the whole. Each module is set different clock signal by phase locked loop technique, and achieved by writing finite state machine and improved counter. The simulation results show that the method meets the requirements of realizing the timing with high precision, and achieves the desired effect with fast speed and high flexibility.

Key words: flat panel detector;analog front end;timing;Verilog;simulation