关键词: HEVC, 运动估计, 六边形搜索, VLSI

Abstract:

Motion Estimation is the most time consuming module in HEVC with high computational complexity. In order to speed up the encoding process, a VLSI architecture of hexagon-based motion estimation search for HEVC is proposed. This architecture can support variable-sized blocks in the HEVC standard and fully considerers the data multiplexing of hexagon search. The PE array uses the pipeline organization strategy to significantly reduce the on-chip cache access times. Using SMIC 65 nm technology, the proposed architecture is synthesized at the maximum operating frequency of 100 MHz with 101 thousand gates. Simulation result shows that the architecture is able to process 1 920 × 1080 p video at 60 f/s.

Key words: HEVC, motion estimation, hexagon based search, VLSI