一种折叠式共源共栅运算放大器的准确设计方法

doi:10.16180/j.cnki.issn1007-7820.2023.03.008

摘要/Abstract

摘要：

传统折叠式共源共栅放大器的人工设计流程只能得到近似的设计结果,优化方法获得的结果较好,但需耗费大量计算。文中针对这类放大器,给出了一种准确设计方法。通过SPICE仿真弥补传统设计流程各性能指标解析近似产生的误差,同时采用基于BSIM模型的器件尺寸计算,反复执行这一设计流程,消除了传统设计过程存在的误差,得到准确的设计结果。文中所提方法相较于传统人工方法更精确,避免了设计时的反复调试;与优化方法相比,虽仍要通过一个迭代过程,但因收敛较快,故计算量较小。文中以0.18 μm与90 nm实际工艺库下的电路设计为例,给出了仿真设计结果,证明了所提方法的正确性与有效性。

关键词: 模拟IC设计, 运算放大器, 模拟设计自动化, 电路优化设计, 器件尺寸, BSIM模型, 共源共栅放大器, 迭代设计方法

Abstract:

The results obtained from the traditional design procedure of the folded cascode amplifier are inaccurate. The optimization method can produce fairly accurate design results, but consumes large amount of computations. This study presents an accurate design method for this kind of amplifier. Through SPICE simulation, the errors caused by the analysis and approximation of various performance indicators in the traditional design process are compensated. At the same time, The device size calculation based on the BSIM model is adopted, and this design process is repeatedly executed, which gradually eliminates the errors existing in the traditional design process and obtains accurate design results. Compared with the traditional manual method, the proposed method is more accurate and avoids repeated debugging during design. When compared with the optimization method, although the proposed design still needs to go through an iterative process, the calculation amount is smaller due to the faster convergence. The circuit design under the actual process library of 0.18 μm and 90 nm is taken as an example, and the simulation experiments proves the correctness and effectiveness of the proposed method.

Key words: analog IC design, operational amplifier, analog design automation, circuit optimization, device sizing, BSIM model, cascode amplifier, iterated design

中图分类号:

TN402

王嘉奇,吕高崇,郭裕顺. 一种折叠式共源共栅运算放大器的准确设计方法[J]. 电子科技, 2023, 36(3): 50-54.

WANG Jiaqi,LÜ Gaochong,GUO Yushun. An Accurate Design Approach for the Folded Cascode Operational Amplifier[J]. Electronic Science and Technology, 2023, 36(3): 50-54.

图/表 9

图1

表1

折叠式共源共栅运算放大器设计流程"

步骤	计算
1	I_d₃=SR×C_L,I_d_1,2= $12$ I_d₃
2	g_m₁=ω_uC_L, $W L 1,2$ = $g m 1 2 μ p C o x (2 I d 1)$
3	$W L 4,5$ = $2 I d 3 μ p C o x V o v 5 2$ , $W L 6,7$ = $2 I d 2 μ p C o x V o v 7 2$ , V_ov₅=V_ov₇= $12 V D D - V o u t, m a x$
4	$W L 3$ = $2 I d 3 μ n C o x V o v 3 2$ ,V_ov₃=V_inc_,_min-V_SS-V_gs₁
5	$W L 8,9, 10,11$ = $2 I d 3 μ n C o x V o v 9 2$ ,V_ov₉= $V o u t, m i n - V S S 2$

表1

图2

表2

折叠式共源共栅运算放大器设计流程"

步骤	计算
1	根据式(17)更新 $I d 3 k + 1$ , $I d 1,2 k + 1$ =0.5 $I d 3 k + 1$ ;
2	根据式(16)更新 $g m 1 k + 1$ ,然后根据式(19)计算 $V g s 1 k + 1$ 、 $W 1 k + 1$ ;
3	根据式(18)计算 W_4,5;
4	根据式(29)更新 $p n d k + 1$ ,然后根据式(32)和式(18)计算L₇和 L₈ ;
5	$V o v 3 k + 1$ =V_inc_,_min-V_SS- $V g s 1 k + 1$ ,根据式(18)计算 W₃;
6	根据式(25)、式(26)更新g_ds₉、g_ds₁₁,然后根据式(28)和式(18)计算L₉、L₁₁以及W₉、W₁₁。

表2

表3

表4

表5

表6

图3

参考文献 17

[1]	Allen P E, Holberg D R. CMOS模拟集成电路设计[M]. 冯军,李智群,译. 2版. 北京: 电子工业出版社, 2013.
	Allen P E, Holberg D R. CMOS analog integrated circuit design[M].Translated by Feng Jun,Li Zhiqun.2nd ed. Beijing: Electronic Industry Press, 2013.
[2]	Stefanovic'D, Kayal M. Structured analog CMOS design[M]. Berlin: Springer Science and Business Media, 2008.
[3]	Mahattanakul J. Design procedure for two-stage CMOS operational amplifiers employing current buffer[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2005, 52(11):766-770.
[4]	Guo Y S. An accurate design approach for two-stage CMOS operational amplifiers[J]. IEEE Asia Pacific Conference on Circuits and Systems, 2016, 7(80):40-49.
[5]	Mallya S, Nevin J H. Design procedures for a fully differential folded-cascode CMOS operational amplifier[J]. IEEE Journal of Solid-State Circuits, 1989, 24(6):1737-1740. doi: 10.1109/4.45013
[6]	Yang H C, Abu-Dayeh M A, Allstot D J. Small-signal analysis and minimum settling time design of a one-stage folded-cascode CMOS operational amplifier[J]. IEEE Transactions on Circuits and Systems, 1991, 38(7):804-807. doi: 10.1109/31.135753
[7]	吴梦维, 王振铎. 基于CMOS集成温度传感器的电路设计与仿真[J]. 电子科技, 2018, 31(8):86-88.
	Wu Mengwei, Wang Zhenduo. Circuit design and simulation based on CMOS integrated temperature sensor[J]. Electronic Science and Technology, 2018, 31 (8):86-88.
[8]	陆序长, 张虎龙, 谢亮, 等. 应用于Sigma-Delta ADC中的高性能前置放大器[J]. 太赫兹科学与电子信息学报, 2018, 16(3):547-551.
	Lu Xuchang, Zhang Hulong, Xie Liang, et al. Design of a high performance pre-amplifier for Sigma-Delta ADC[J]. Journal of Terahertz Science and Electronic Information Technology, 2018, 16(3):547-551.
[9]	Kurwade D, Mali M B. Design of high gain bandwidth CMOS operational amplifier[J]. Digital Signal Processing, 2018, 10(7):116-119.
[10]	梁广磊, 张红旗, 林军. 一种运算放大器低温条件下自激振荡机理分析[J]. 电子科技, 2017, 30(11):9-12.
	Liang Guanglei, Zhang Hongqi, Lin Jun. Analysis of the mechanism of self-excited oscillation at low temperature of an operational amplifier[J]. Electronic Science and Technology, 2017, 30(11):9-12.
[11]	Pollissard-Quatremère G, Gosset G, Flandre D. A modified gm/ID design methodology for deeply scaled CMOS technologies[J]. Analog Integrated Circuits and Signal Processing, 2014, 78(3):771-784. doi: 10.1007/s10470-013-0166-z
[12]	Aminzadeh H. Systematic circuit design and analysis using generalized gm/ID functions of MOS devices[J]. IET Circuits, Devices & Systems, 2020, 14(4):432-443. doi: 10.1049/cds2.v14.4
[13]	程俊明, 张铁笛, 延波, 等. 基于CMOS的96-105 GHz太赫兹放大器的设计[J]. 微波学报, 2020, 36(S1):312-314.
	Cheng Junming, Zhang Tiedi, Yan Bo, et al. A 96-105GHz terahertz amplifier design in CMOS process[J]. Journal of Microwaves, 2020, 36(S1):312-314.
[14]	Çiçekli H, Karacan Í, Gökçen A. Current operational amplifier based voltage-mode MOS-C all-pass filter and its application[J]. Politeknik Dergisi, 2020, 23(2):409-414.
[15]	张春茗, 严展科, 王梦海, 等. 一种驱动大容性负载的三级运算放大器[J]. 微电子学, 2019, 49(5):613-617.
	Zhang Chunming, Yan Zhanke, Wang Menghai, et al. A three-stage operational amplifier for driving large capacitive loads[J]. Microelectronics, 2019, 49(5):613-617.
[16]	Wang J, Adhikari G, Tsukiji N, et al. Analysis and design of operational amplifier stability based on routh-hurwitz stability criterion[J]. IEEJ Transactions on Electronics, Information and Systems, 2018, 138(12):1517-1528. doi: 10.1541/ieejeiss.138.1517
[17]	Asaithambi S, Rajappa M, Ravi L. Optimization and control of CMOS analog integrated circuits for cyber-physical systems using hybrid grey wolf optimization algorithm[J]. Journal of Intelligent & Fuzzy Systems, 2019, 36(5):4235-4245.

	A_v/dB	UGB/MHz	PM/(°)	SR/V·μs^-1
设计指标	65.00	150.00	65.00	110.00
初始指标	66.25	127.30	63.71	90.68
设计结果	65.08	149.60	65.12	109.90

	A_v/dB	UGB/MHz	PM/(°)	SR/V·μs^-1
设计指标	55.00	80.00	65.00	60.00
初始指标	52.80	72.81	81.25	51.62
设计结果	54.91	79.84	65.02	59.91

MOS管	W/L:μm/μm	MOS管	W/L:μm/μm
M_1,2	19.70/0.40	M_6,7	89.63/0.30
M₃	3.02/0.40	M_8,9	20.15/0.42
M_4,5	230.55/0.40	M_10,11	5.36/0.41

MOS管	W/L:μm/μm	MOS管	W/L:μm/μm
M_1,2	5.32/0.40	M_6,7	14.12/0.81
M₃	3.91/0.40	M_8,9	19.39/0.47
M_4,5	94.67/0.40	M_10,11	0.75/0.52