关键词: 可逆逻辑电路, 硬件描述语言, 可逆算术逻辑单元, 仿真验证

Abstract:

The high level abstract description capability of the hardware description language and simulation capability of the current EDA platform are combined to resolve the bottleneck in the design of largescale reversible logic circuits by reversible logic synthesis. Service bits are added to the module, which offers the module both a corresponding function and reversibility. The module is also instantiated for the reversible arithmetic logic unit to be described and synthesized. The simulations show that the proposed method is feasible and effective.

Key words: reversible logic circuit, hardware description language, reversible arithmetic logic unit, simulation verification