Abstract:

Matrix decomposition is one of the important operations in matrix inversion, which is widely used in neural networks, digital signal processing, wireless communication technology and other fields. Based on a column-vector optimized QR decomposition algorithm, this study proposes a one-dimensional linear matrix decomposition structure and completes the ASIC implementation of the structure to address the shortcomings of the traditional decomposition algorithm operations that are not conducive to hardware implementation. The matrix decomposer supports matrix decomposition operations of order 2~32 and operates at 700 MHz at TSMC 28 nm process. Simulation and FPGA test results show that the relative error between the decomposer and MATLAB results is less than 10^-12. When performing matrix decomposition of more than 12-orders, the operation cycle of the decomposer has a speedup ratio of 2.3 times compared with the traditional one-dimensional linear structure. When performing 32-order matrix decomposition, the operation cycle of the decomposer has a speedup ratio of 22.8 times compared with NIVIDA RTX2070.

Key words: matrix decomposition, QR decomposition, Givens rotation, Column-wise Givens Rotation, FPGA implementation, hardware acceleration, one-dimensional linear structure, ASIC implementation