Abstract:

This paper introduces the layout design of electronic products panel controller chip during Huahong NEC 0.35 μm CZ6H 1P3AL process by SOC Encounter.In the layout design,a good placing effect is achieved by using time-driven placement and limiting placement density.A combination of clock tree automatic synthesis and manual modification reduces the clock skew to the minimum degree.Problems resulting from power network connection and routing violations are solved.At last,the chip meets the demand of both timing and technology,reaching the following target: the working frequency of 12 MHz,the chip area of 1.089 mm² and the power dissipation of 2.715 2 mW.

Key words: electronic products panel controller chip;Floorplanning;placement and routing;clock tree synthesis;design for manufacturability