LDPC码的级联译码算法的改进与实现

Abstract

Abstract:

An FPGA implementation scheme for the OSD serially concatenated decoding algorithms is proposed for LDPC codes with short or moderate code length.Our scheme implements the GF(2) Gaussian elimination used in OSD algorithm based on the block RAM resource of the FPGA chip,which avoids the large quantity of logic resource demand for the conventional implementation of GF(2) Gaussian elimination.Implementation result shows that the concatenated decoder with 500 kbit·s^-1 throughput can be achieved on middle and low grade FPGA using this scheme.

Key words: channel coding;low density parity-check code;reliability decoding;log-likelihood ratio accumulation;field programmable gate arrays

CLC Number:

TN911.22

CHEN Meng. Improvement and Implementation of Concatenated Decoding for LDPC Codes[J]., 2014, 27(6): 156-.

References

［1］RICHARDSON T J,URBANKE R L.The capacity of low-density parity-check codes under message-passing decoding［J］.IEEE Transactions on Information Theory,2001,47(2):599-618.

［2］FOSSORIER M.Iterative reliability-based decoding of low-density parity check codes［J］.IEEE Journal on Selected Areas in Communications,2001,19(5):908-917.

［3］GOUNAI S,OHTSUKI T.Lowering error floor of irregular LDPC codes by CRC and OSD algorithm［J］.Ieice Transactions on Communications,2006,E89B(1):1-10.

［4］JIANG M,ZHAO C M,XU E Y,et al.Reliability-based iterative decoding of LDPC codes using likelihood accumulation［J］.IEEE Communications Letters,2007,11(8):677-679.

［5］LI G W,FENG G Z.Generalised reliability-based syndrome decoding of LDPC codes［J］.European Transactions on Telecommunications,2008,19(8):873-877.

［6］BIAN Y B,FENG G Z.A novel concatenation decoding algorithm for short LDPC codes with lower complexities［C］.Proceedings of 2009 Conference on Communication Faculty,2009:550-554.

［7］董自健,酆广增.一种基于缩减伴随式集的QC-LDPC码级联译码算法［J］.电子与信息学报,2010,32(4):825-829.

［8］董自健,酆广增.基于伴随式的OSD改进算法［J］.南京邮电大学学报:自然科学版,2011(1):35-38.

［9］TONG S,ZHENG H J.On combining chase-2 and sum-product algorithms for LDPC codes［J］.Etri Journal,2012,34(4):629-632.

［10］QIAO G L.Parallel decoding scheme based on OSD and KNIH algorithms［J］.Materials Science and Information Technology,2012(43):4813-4816.

［11］BOGDANOV A,MERTENS M C,PAAR C,et al.A parallel hardware architecture for fast gaussian elimination over GF(2)［C］.14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines,Proceedings,2006:237-246.

［12］ZHANG B W,GU G C,SUN L,et al.Floating-point FPGA gaussian elimination in reconfigurable computing system［J］.Chinese Journal of Electronics,2011,20(1):51-54.

［13］ZTE,CATT,RITT,Huawei.R1-051070-comparison of structured LDPC codes and 3GPP turbo codes［S］.Sandiego USA:3GPP TSG RAN WG1 #42bis,2005.

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Improvement and Implementation of Concatenated Decoding for LDPC Codes

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