›› 2014, Vol. 27 ›› Issue (6): 39-.

• Articles • Previous Articles     Next Articles

Design of a Sampling Clock with Low Phase Noise

JIANG Xiaoqiang,SHI Yu,SU Angang,ZHAO Baolin   

  1. (School of Microelectronics and Solid Electronics,University of Electronic Science and Technology of China,Chengdu 610054,China)
  • Online:2014-06-15 Published:2014-06-14

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Abstract:

This paper introduces the theories of phase locked loop and direct digital synthesis,discusses their advantages and disadvantages,and presents the design of a sampling clock with low phase noise using the PLL and DDS technologies.The measurement results show that the phase noise is up to -119 dBc@1 kHz and -116 dBc@100 kHz at 70 MHz.

Key words: phase locked loop;digital direct synthesis;filter;phase noise

CLC Number: 

  • TN74+2.1

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