基于PCIE的多嵌入式人工智能处理器低延迟数据交换技术

doi:10.16180/j.cnki.issn1007-7820.2024.05.005

Abstract

Abstract:

In view of the conflict of task scheduling and data exchange between multiple embedded AI(Artificial Intelligence) processors and improving the reliability and efficiency of stack expansion of multiple AI processors, a high speed data exchange technology and data frame structure of multiple embedded AI processors with wormhole switching structure are proposed in this study. Based on the PCIE(PCI Express) high-speed data interface, the data is transmitted in the form of data unit, and the multi-weight decision algorithm is designed to avoid the conflict in data transmission and realize the concurrent multi-threading of the task.The FPGA(Field Programmable Gate Array) platform is designed and tested. The results show that the transmission bandwidth utilization efficiency of PCIE reaches more than 85%, the data exchange delay is less than 20 μs, and the average maximum delay time of interrupt task response is 8.775 μs.The technology is suitable for high-speed switching circuits with multi-processor collaboration and can be extended to hybrid PCIE and RapidIO switching circuit architectures.

Key words: embedded AI processors, data exchange, fast peripheral component interconnection, PCI Express, exchange switch, wormhole technology, data arbitration, multi-weighted decision making

CLC Number:

TN919

WEI Xuan, WEN Kailin, LI Bin, LIU Shutao, CHU Jie, CAI Jueping. Multiple Embedded AI Processors Low Latency Data Exchange Technology Based on PCIE Interface[J].Electronic Science and Technology, 2024, 37(5): 32-37.

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References 18

[1]	Linley G. Qualcomm samples first AI chip[J]. Microprocessor Report, 2020, 34(10):11-13.
[2]	张玄, 张多利, 宋宇鲲. 异构多核SoC处理器内部存储架构优化[J]. 电子科技, 2022, 35(9):44-51.
	Zhang Xuan, Zhang Duoli, Song Yukun. Optimization of the internal memory architecture of heterogeneous multicore SoC processors[J]. Electronic Science and Technology, 2022, 35(9):44-51.
[3]	Fetanat M, Stevens M, Jain P, et al. Fully elman neural network:A novel deep recurrent neural network optimized by an improved Harris hawks algorithm for classification of pulmonary arterial wedge pressure[J]. IEEE Transactions on Biomedical Engineering, 2022, 69(5):1733-1744.
[4]	Gwennap L. Huawei ascends in AI accelerators[J]. Microprocessor Report, 2019, 33(5):4-5.
[5]	王元强, 聂云杰, 朱孟江. 一种基于FPGA的PCIe总线高速异步传输系统[J]. 单片机与嵌入式系统应用, 2018, 18(8):62-64+68.
	Wang Yuanqiang, Nie Yunjie, Zhu Mengjiang. High-speed asynchronous transmission system based on FPGA PCIe bus[J]. Microcontrollers and Embedded Systems, 2018, 18(8):62-64,68.
[6]	王宏, 霍银龙. 一种基于FPGA和PCIe总线的数据传输机制研究[J]. 电工技术, 2021, 39(2):91-93.
	Wang Hong, Huo Yinlong. Research on data transmission mechanism based on FPGA and PCIe bus[J]. Electronic Engineering, 2021, 39(2):91-93.
[7]	赵姣. PCIE交换芯片的交换核心设计[J]. 中国集成电路, 2020, 29(3):72-79,93.
	Zhao Jiao. Core design of PCIE switch[J]. China Integrated Circuit, 2020, 29(3):72-79,93.
[8]	韩强. 基于PCI Express总线架构的多处理器模块设计[J]. 信息通信, 2018(5):137-139.
	Han Qiang. Design of multi-processor module based on PCI Express bus architecture[J]. Information and Communications, 2018(5):137-139.
[9]	张锋印, 高博, 冀亚玮. 基于FPGA的多应用任务流量管理算法[J]. 电子科技, 2022, 35(12):7-23.
	Zhang Fengyin, Gao Bo, Ji Yawei. Multi-task traffic management algorithm based on FPGA[J]. Electronic Science and Technology, 2022, 35(12):7-23.
[10]	赵二虎, 吴济文, 查晶晶, 等. 基于ARM+DLP+SRIO的嵌入式智能计算系统研究[J]. 电子学报, 2021, 49(3):443-453. doi: 10.12263/DZXB.20200415
	Zhao Erhu, Wu Jiwen, Zha Jingjing, et al. Embedded AI computing system based on ARM+DLP+SRIO[J]. Acta Electronica Sinica, 2021, 49(3):443-453. doi: 10.12263/DZXB.20200415
[11]	傅凌峰. PCI Express桥接电路交换核心的设计与研究[D]. 西安: 西安电子科技大学, 2018:1-60.
	Fu Lingfeng. Design and research of PCI Express bridge circuit switching core[D]. Xi'an: Xidian University, 2018:1-60.
[12]	王文清, 张金. 基于RIFFA架构的PCIE多通道高速传输系统设计[J]. 自动化与仪表, 2020, 35(11):61-64.
	Wang Wenqing, Zhang Jin. Design of PCIE multi-channel high-speed transmission system based on RIFFA architecture[J]. Automation and Instrumentation, 2020, 35(11):61-64.
[13]	王炳辉, 何小海, 卿粼波, 等. 基于FPGA的DMA数据传输系统设计[J]. 电子设计工程, 2020, 28(8):26-30.
	Wang Binghui, He Xiaohai, Qing Linbo, et al. Design of DMA data transmission system based on FPGA[J]. Electronic Design Engineering, 2020, 28(8):26-30.
[14]	栗永强, 张永坡, 布乃红. 基于FPGA的DDR存储器突发读取设计技术[J]. 国外电子测量技术, 2016, 35(6):51-54.
	Li Yongqiang, Zhang Yongpo, Bu Naihong. Design technology of burst reading to DDR memory based on FPGA[J]. Foreign Electronic Measurements Technology, 2016, 35(6):51-54.
[15]	葛裴. 数据通信交换技术的现状分析[J]. 通信电源技术, 2021, 38(4):189-191.
	Ge Pei. On data communication and exchange technology and application[J]. Telecom Power Technologies, 2021, 38(4):189-191.
[16]	吴陶迪, 孙自强. 基于虫孔直通交换片上网络的共享优先级机制[J]. 华东理工大学学报(自然科学版), 2017, 43(2):254-259,285.
	Wu Taodi, Sun Ziqiang. A shared priority policy in wormhole cut-through switching based network-on-chip[J]. Journal of East China University of Science and Technology(Natural Science Edition), 2017, 43(2):254-259,285.
[17]	张婷, 李文敬. 基于多核PC的事务内存冲突管理算法的改进[J]. 现代计算机, 2019, 8(23):3-8,23.
	Zhang Ting, Li Wenjing. Improvement of transaction memory conflict management algorithm based on multicore[J]. Modern Computer, 2019, 8(23):3-8,23.
[18]	李龙乾, 方华, 冯姣, 等. 基于FPGA的PCIe接口逻辑设计与实现[J]. 太赫兹科学与电子信息学报, 2022, 20(4):385-392.
	Li Longqian, Fang Hua, Feng Jiao, et al. Design and implementation of PCIe interface logic based on FPGA[J]. Journal of Terahertz Science and Electronic Information Technology, 2022, 20(4):385-392.

中断向量数目	最小延迟时间/μs	最大延迟时间/μs
1	5.7	6.5
2	5.8	6.5
3	6.2	6.8
4	6.2	7.3
平均延迟时间	6.0	6.8

Multiple Embedded AI Processors Low Latency Data Exchange Technology Based on PCIE Interface

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[3]	LI Huang, GONG Feng, CHEN Yan-Hua. Data Transmission Card Based on the PCIE Driver [J]. , 2014, 27(1): 117-.
[4]	PENG Yang,MENG Lilin,LI Nian,LI Li. Design and Implementation of the High-speed Encryption Card Based on FPGA [J]. , 2013, 26(6): 42-.
[5]	XIE Li-Bin, LIU Kai, SHANG Yu. Research on Serial RapidIO Switch Technologies [J]. , 12, 25(9): 129-.