一种采用互连线电容耦合的线计算电路设计

doi:10.19665/j.issn1001-2400.2022.03.024

Abstract

Abstract:

With the continuous development of integrated circuit technology nodes,the influence of the parasitic effect between interconnects becomes more and more obvious.The interconnection line has become one of the key factors restricting the ability of chip computing,and the design method of using the interconnection line as logical calculation has aroused the designer's wide concern.Based on the study of the coupling effect of capacitance between metal interconnectors,a circuit scheme which uses the deterministic signal interference between metal interconnectors to carry out logic calculation is proposed.First,the capacitive coupling relationship between metal interconnections is analyzed to construct a capacitive coupling model.Then nano metal wires are used to form coupling capacitors,and further to design NAND,NOR,XOR and XNOR gates by adjusting the coupling strength between the interference line and the victim line and adjusting the inverter threshold.After that,a 3-wire-8-wire decoder based on capacitive coupling of interconnection lines is realized.Finally,by using TSMC 65 nm CMOS technology for simulation verification under Cadence Spectre environment,the results show that the designed line calculation circuit functions correctly.Compared with the standard unit of the TSMC 65 nm technology library,the number of transistors used in the two-input line calculation NAND is reduced by 25%,the power consumption of the two-input line calculation XNOR is reduced by 29.1%,and the area and power delay product of the four-input line calculation NAND are reduced by 46.4% and 55%,respectively.Therefore,the line calculation logic gate has the characteristics of a low hardware overhead,thus providing a new way to realize digital integrated circuits intensively,which is conducive to the miniaturization of chips.

Key words: capacitive coupling, metal interconnection line, line calculation, logic gate, decoder

CLC Number:

TN402

LI Lin,ZHANG Huihong,ZHANG Yuejun. Design of the line calculation circuit based on capacitive coupling of interconnection lines[J].Journal of Xidian University, 2022, 49(3): 213-221.

Figures/Tables 11

References 19

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来源	电路	工艺 /nm	晶体管数量/个	面积 /μm²	供电电压 /V	平均功耗 /μW	传输延迟 /ps	功耗延时积 /aJ	线计算
文献[18]	NAND	90	9		0.3		180.0		否
文献[18]	NOR	90	9		0.3		187.5		否
文献[19]	NOR	90	20		0.3		50.0		否
	ND2D0	65	4	1.440	1.2	0.60	12.5	7.500	否
台积电65 nm	NR2D0	65	4	1.440	1.2	0.71	14.0	9.940	否
工艺库	XNR2D0	65	12	3.600	1.2	2.85	50.0	142.500	否
	ND4D0	65	8	2.520	1.2	1.30	28.5	37.050	否
	ND2D0	65	3	1.350	1.2	0.47	6.5	3.055	是
	NR2D0	65	3	1.350	1.2	0.91	29.5	26.845	是
笔者所提	XOR2D0	65	8	3.708	1.2	2.25	113.0	254.250	是
	XNR2D0	65	8	3.708	1.2	2.02	26.0	52.520	是
	ND4D0	65	3	1.350	1.2	1.19	14.0	16.660	是
	3线-8线译码器	65	47	22.104	1.2	17.06	87.0	1 484.220	是

Design of the line calculation circuit based on capacitive coupling of interconnection lines

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