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Low power design of the embedded 64kb SRAM based on the DBL approach

FENG Guo-chen;LIU Xing-wang;SHEN Xu-bang

  

  1. (Xi′an Microelectronic Technology Institute, Xi′an 710054, China)
  • Received:1900-01-01 Revised:1900-01-01 Online:2005-08-20 Published:2005-08-20

Abstract: To meet the low power requirement of the embedded system, a 64kb-embedded SRAM module is designed by adopting the DBL approach and the proposed memory array Divided Block Decoding approach. Compared with the common memory structure, the power decreases by 43%, while the area increases only by 18%.

Key words: memory, SRAM, divided bit line, divided block decoding

CLC Number: 

  • TP343