一种高速高宽带主从式采样保持电路

doi:10.3969/j.issn.1001-2400.2018.04.022

Abstract

Abstract:

This paper presents a new-style high-speed broadband master-slave sampling and hold circuit based on the 0.13μm SiGe BiCMOS. In order to realize DC coupling and sample the low-frequency low-offset-voltage signal, the PMOS source follower is used in the input stage. The Cherry-Hooper structure is used to expand the bandwidth up to 18GHz. Signal feedthrough is cancelled by the master-slave sampling structure and cross-coupled capacitors. Clock feedthrough is attenuated by complementary bipolar transistors. The spurious free dynamic range is 33～38dB. Comparison results show that the proposed circuit has a big advantage in bandwidth and is able to sample at a high sampling rate.

Key words: high-speed and high-broadband, master-slave sampling structure, sample-and-hold circuit, signal feedthrough, clock feedthrough, analog-to-digital converter

DING Hao;WANG Jianye;LIU Wei;XIONG Yongzhong. High-speed high-broadband master-slave sampling and hold circuit[J].Journal of Xidian University, 2018, 45(4): 123-128.

References

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High-speed high-broadband master-slave sampling and hold circuit

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