关键词: 快速傅里叶变换, 可配置, 现场可编程门阵列

Abstract:

A reconfigurable IP core implemented on FPGA is described.This FFT architecture is based on a butterfly process which employs pipeline architecture and fast parallel multiplier.An implementation of 4k points based on this IP with the reconfigurable points,data width and radix is performed.This IP is realized by Verilog and simulated by ModelSim.It is synthesized by ISE and downloaded to Virtex-5 xc5vfx70t that runs at 200 MHz clock.The experimental result and performance comparison show that it has better capability and speed than exiting reported realizations.

Key words: FFT;re configuration;FPGA