›› 2015, Vol. 28 ›› Issue (9): 70-.

• 论文 • 上一篇    下一篇

一种片内集成飞电容的自适应开关电容DC-DC

魏榕山,代明   

  1. (福州大学 物理与信息工程学院,福建 福州 350116)
  • 出版日期:2015-09-15 发布日期:2015-09-15
  • 作者简介:魏榕山(1980—),男,博士,副教授。研究方向:微纳电子器件与集成电路设计。E-mail:wrs08@fzu.edu.cn。代明(1988—),男,硕士研究生。研究方向:集成电路设计。
  • 基金资助:

    国家自然科学基金资助项目(61404030)

An Auto-reconfigurable Switched-capacitor DC-DC with On-Chip Fly-Capacitor

WEI Rongshan,DAI Ming   

  1. (College of Physics and Information Engineering,Fuzhou University,Fuzhou 350116,China)
  • Online:2015-09-15 Published:2015-09-15

摘要:

提出一种电容片内集成、高效率升压模式的DC-DC电源管理芯片,较普通结构相比,文中提出的电路结构具有6组2×,3组3×,2组4×升压模型共11种工作模式,并具有低纹波等优点。通过MIM电容与积累型NMOS电容串联的方式,提高单位面积容值,使得总电容面积大幅减小。采用SMIC 0.18μm CMOS工艺,利用Cadence工具对电路进行仿真验证,所提出自适应开关电容升压电路,在输出电压为3 V时,其效率最高可达到83.6%。在开关频率为20 MHz时,输入电压范围为1~1.8 V,所需总片内集成电容总面积为900 μm×900 μm,输出电压纹波<40 mV

关键词: DC DC, 高效率, 集成电容

Abstract:

A high-efficiency boost mode electronic power management chip with on-chip capacitor is proposed.Compared to the conventional structure,the presented circuit has 11 patterns:six groups of 2×,3 groups of 3×,and 2 groups of 4× booster modes.It also has the advantage of low-ripple and so on.The chip size is greatly reduced by using MIM capacitance and accumulation NMOS capacitance in series,which increases the capacity value per unit area.The proposed circuit is implemented using SMIC 0.18 μm CMOS process.The Cadence simulation results show that the efficiency is up to 83.6% when the output voltage is 3 V.When the switching frequency is 20 MHz with the input voltage from 1 V to 1.8 V,the area of overall capacitor integrated on chip is 900 μm×900 μm and the output ripple is less than 40 mV.

Key words: DC DC;high efficiency;on chip capacitor

中图分类号: 

  • TN63+.1