一种高性能极化码SC译码器设计

doi:10.16180/j.cnki.issn1007-7820.2022.08.003

Abstract

Abstract:

In view of high latency, low throughput and low area efficiency of polar code SC decoder, a high-performance hardware architecture of SC decoder is proposed. The decoder becomes low-latency and high-throughput by pruning frozen bit nodes to simplify the SC decoding binary tree, designing cross-cycle storage for PE, and using 2b-SC algorithm in the last stage. The resource-reused method is adopted to increase the decoder area efficiency. The testing results show that the cycle of the proposed decoder is 330, the throughput is 388.85 Mbit·s^-1, and the area efficiency is 2.204 Mbit·s^-1·kGE^-1. Compared with other SC decoders, latency, throughput and area efficiency of the high-performance SC decoder proposed in this study are significantly improved. Additionally, the decoder has lower power consumption and broad application prospect.

Key words: polar code, successive cancellation, latency, power consumption, throughput, area efficiency, resource reuse, ASIC

CLC Number:

TN47

WANG Xiaolei,DAI Wujun,DU Gaoming,LI Zhenmin,ZHANG Duoli. Design of a High-Performance SC Decoder for Polar Codes[J].Electronic Science and Technology, 2022, 35(8): 14-20.

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References 19

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冻结信号		使能信号		输入		输出
fr₁	fr₂	en₁	en₂	LLR(a)	LLR(b)	u_odd	u_even
0	0	1	0	MSB(a)MSB(b)=1		0	MSB(a)
0	0	1	0	MSB(a)MSB(b)≠0		1	MSB(b)
1	0	0	1	LLR(a)+LLR(b)<0		0	1
1	0	0	1	LLR(a)+LLR(b)≥0		0	0
x	1	0	0	x	x	0	0

数据类型	结果
工艺/nm	40
频率/MHz	250.6
效率/ Mbit·s^-1·kGE^-1	2.204
电压/V	1.21
面积/mm²	0.18
电路门数/kGE	176.46
吞吐率/ Mbit·s^-1	388.85

设计	文献[15]	文献[16]	文献[17]	本文
算法	SC	SC	SC	SC
工艺/nm	180	180	180	180
架构	parallel	Tree	Tree	Line
频率/MHz	150.0	446.7	337.0	222.2
周期/clk	1 560	1 534	1 534	330
吞吐率/ Mbit·s^-1	49	149	126	343.60
电路门数/kGE	183.64	295.44	256.34	176.46
面积/mm²	1.71	5.35	-	2.19
效率/ Mbit·s^-1·kGE^-1	0.267	0.505	0.492	1.949

数据类型	文献[15]	文献[16]	本文
工艺/nm	180	180	180
电压/V	1.50	1.80	1.61
功耗/mW	67.0	1 072.9	200.0

Design of a High-Performance SC Decoder for Polar Codes

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