Electronic Science and Technology ›› 2022, Vol. 35 ›› Issue (8): 14-20.doi: 10.16180/j.cnki.issn1007-7820.2022.08.003

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Design of a High-Performance SC Decoder for Polar Codes

WANG Xiaolei,DAI Wujun,DU Gaoming,LI Zhenmin,ZHANG Duoli   

  1. Institute of VLSI Design,Hefei University of Technology,Hefei 230601,China
  • Received:2021-03-10 Online:2022-08-15 Published:2022-08-10
  • Supported by:
    National Key R&D Program(2018YFB2202604);University Synergy Innovation Program of Anhui(GXXT-2019-030)


In view of high latency, low throughput and low area efficiency of polar code SC decoder, a high-performance hardware architecture of SC decoder is proposed. The decoder becomes low-latency and high-throughput by pruning frozen bit nodes to simplify the SC decoding binary tree, designing cross-cycle storage for PE, and using 2b-SC algorithm in the last stage. The resource-reused method is adopted to increase the decoder area efficiency. The testing results show that the cycle of the proposed decoder is 330, the throughput is 388.85 Mbit·s-1, and the area efficiency is 2.204 Mbit·s-1·kGE-1. Compared with other SC decoders, latency, throughput and area efficiency of the high-performance SC decoder proposed in this study are significantly improved. Additionally, the decoder has lower power consumption and broad application prospect.

Key words: polar code, successive cancellation, latency, power consumption, throughput, area efficiency, resource reuse, ASIC

CLC Number: 

  • TN47