基于RRAM双交叉阵列结构的三值存内逻辑电路设计

doi:10.16180/j.cnki.issn1007-7820.2022.04.002

Abstract

Abstract:

Implementing logic within RRAM crossbar is an attractive approach to overcome the memory wall in conventional Von Neumann architecture. Ternary logic can reduce the number of logic operations and enhance the computation speed compared to binary logic. In this study, a ternary logic-in-memory scheme is proposed based on the RRAM dual-crossbar structure, in which the inputs and outputs are represented by the multi-level cells of RRAMs. Two ternary logic gates and one binary logic gate are supported in the proposed structure to effectively increase the computation speed. Experimental results show that the operation steps of the ternary logic-in-memory adder are reduced by up to 68.84%, as compared with previously published binary logic-in-memory designs. The energy consumed by the ternary logic-in-memory adder is also reduced by 33.05% when compared with previously published IMPLY-based design.

Key words: ternary logic-in-memory, memory wall, resistive random-access memory, RRAM crossbar, multi-level cell, hybrid CMOS-MLC, ternary adder, carbon nanotube transistors

CLC Number:

TN47

Weiyi LIU,Yanan SUN,Weifeng HE. Design of Ternary Logic-in-Memory Based on RRAM Dual-Crossbars[J].Electronic Science and Technology, 2022, 35(4): 8-13.

Figures/Tables 10

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Table 1

Table 2

The truth table of unary operators"

InputA	A⁰	A¹	A²	$A 0 ¯$	$A 1 ¯$	$A 2 ¯$
0	2	0	0	0	2	2
1	0	2	0	2	0	2
2	0	0	2	2	2	0

Table 2

Figure 8.

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存内逻辑电路设计	64位二值加法器/41位三值加法器
存内逻辑电路设计	和的范围	步数	能耗/pJ
文献[10](MAGIC)	3.69×10¹⁹	836	515.07
文献[6](IMPLY)	(N_b= 64)	1088	980.20
本文三值电路	7.29×10¹⁹ (N_t= 41)	339	656.24

Design of Ternary Logic-in-Memory Based on RRAM Dual-Crossbars

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