高速广义多载波解调的低成本硬件优化设计

doi:10.3969/j.issn.1001-2400.2011.03.028

Abstract

Abstract:

Based on GMC (Generalized Multi-carrier)demodulation, a 512 point pipelined IFFT processor is proposed, whose output sequence is consistent with the input sequence of the polyphase filter, thus avoiding the extra data storage and reducing the hardware cost and latency of the whole system. The processor takes a new radix 2³ SDLF (Single-path Delay Locally Feedback) architecture as the basic operating unit, which has a sequence input and a sequence output. After three stages' operation and a buffer with the depth of 64, the processor's final output is the extraction of IFFT results by factor of 8. In the design, a method for extracting the common factor is also proposed to opimize twiddle factor storage. The verification, based on the FPGA, indicates that the proposed processor can reduce the memory size by 30% and 67% respectively, compared with the traditional radix 2³ SDF (Single-path Delay Feedback) and radix 8 FF (Feed Forward) architecture, and reduce output latency by about 43%, compared with the SDF architecture.

Key words: generalized multi-carrier, fast Fourier transform, single-path delay locally feedback, pipelined, twiddle factor

XIONG Herui；HAO Xuefei；HU Guorong. Low-cost hardware optimization design for high-speed GMC demodulation[J].J4, 2011, 38(3): 169-174.

References

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Low-cost hardware optimization design for high-speed GMC demodulation

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