Abstract: This paper presents a novel low-power address bus encoding method to reduce the transition activity on address buses and hence reduce power dissipation. The irredundant sorting bus encoding method reduces the power dissipation of highly capacitive memory address bus based on the dynamic reordering of the modified offset address bus lines. This method reorders the ten least significant bits of offset address according to the value of offset address, and the optimal sorting pattern is transmitted through the high bits of bus without the need for redundant bus lines. As compared to the conventional encoding methods, the proposed encoding method is superior in terms of transition activity reduction on the address bus. Experimental results by using an instruction set simulator and SPEC2000 benchmarks show that the irredundant sorting bus encoding method can reduce signal transitions on the address bus by 88. 2%, and that the power dissipation of the address bus is reduced by 76. 1%, which indicates that the proposed encoding method is very practical for power optimization of the address bus.

Key words: low-power, offset address, address bus, bus encoding, transition activity