Electronic Science and Technology ›› 2019, Vol. 32 ›› Issue (8): 41-45.doi: 10.16180/j.cnki.issn1007-7820.2019.08.009

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Reconfiguration Design of Digital PLL in Carrier Synchronous


  1. School of Information Systems Engineering,Information Engineering University,Zhengzhou 450000,China
  • Received:2018-07-31 Online:2019-08-15 Published:2019-08-12
  • Supported by:
    Natural Science Foundation of Henan(162300410333)


Aiming at the problem that the development efficiency of the code or device in the previous carrier synchronous phase-locked loop is inherited and non-portable, a scheme of reconfiguring carrier synchronous PLLs in the form of reusing FPGA components was proposed. The scheme extracted the common modules of different phase-locked loops through functional decomposition, mapped suitable algorithms for functional modules and implemented them in FPGA. The method used the OCP protocol to encapsulate the interface to generate the FPGA component, and finally reused component to construct a new phase-locked loop application. The simulation results showed that the component reuse rate exceeded 60%, proving the correctness and effectiveness of the new method.

Key words: reconfiguration, digital PLL, carrier synchronous, component, OCP, FPGA

CLC Number: 

  • TN876.4