异构多核SoC处理器内部存储架构优化

doi:10.16180/j.cnki.issn1007-7820.2022.09.007

Abstract

Abstract:

The performance of microprocessors has been greatly improved by the development of heterogeneous multi-core technology. The bandwidth difference between the processor and external memory severely limits the performance of the processor, and the "Memory Wall" problem is becoming increasingly serious. For a heterogeneous multi-core SoC system in high-density computing, this study proposes a set of memory design scheme. The solution increases memory access bandwidth and reduces the frequency of accessing external memory by reusing some local free memory resources that have been idle for a long time as shared L2 cache. Meanwhile, the distributed high-speed shared L2 cache combined with the hierarchical storage structure of multi-channel parallel access to external storage alleviates the speed difference between system processing data and external storage, improves data access efficiency, and optimizes system performance. In terms of resource consumption and computing efficiency, the proposed design saves 69.36% of on-chip SRAM resources compared with ordinary L2 cache, provides 41.2% speedup ratio compared with non-cache structure, and reduces the overall task calculation time by about 40.6% on average.

Key words: heterogeneous multicore, memory wall, multiplexing, multiplexed parallelism, hierarchical memory, L2 cache, distributed, external memory

CLC Number:

TN47

ZHANG Xuan,ZHANG Duoli,SONG Yukun. Optimization of the Internal Memory Architecture of Heterogeneous Multi-Core SoC Processors[J].Electronic Science and Technology, 2022, 35(9): 44-51.

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任务类型	占用数据通道资源	功能类型
Data_type0_mc	网络与外部主存侧数据通道	主控指令信息
Data_type0_rcu	网络与外部主存侧数据通道	RCU指令执信息
Data_type0	网络与外部主存侧数据通道	普通数据读出
Data_type1	网络与外部主存侧数据通道	普通类型数据广播
Data_type2	网络与外部主存侧数据通道	普通类型数据写入
Data_type3	网络与二级缓存侧数据通道	读缓存数据
Data_type4	网络与二级缓存侧数据通道	写缓存数据

实验组号	实验名称	RCA	实验特征
实验1	矩阵转置	0	没有计算需求,DDR无空闲带宽
实验2	简单运算	<1	FFT为共享存储,DDR有空闲带宽
实验3	复杂运算	>1FFT	为私有存储,DDR有空闲带宽

逻辑资源	本文	文献[7]	文献[10]
Slice LUTs	85 525(6.99%)	70 146(5.74%)	96 555(7.90%)
Slice register	112 563(4.60%)	104 133(4.26%)	101 316(4.10%)
Block RAM36	110(8.50%)	359(27.79%)	110(8.50%)

Optimization of the Internal Memory Architecture of Heterogeneous Multi-Core SoC Processors

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