Electronic Science and Technology ›› 2022, Vol. 35 ›› Issue (9): 44-51.doi: 10.16180/j.cnki.issn1007-7820.2022.09.007

Previous Articles     Next Articles

Optimization of the Internal Memory Architecture of Heterogeneous Multi-Core SoC Processors

ZHANG Xuan,ZHANG Duoli,SONG Yukun   

  1. School of Electronic Science and Applied Physics,Hefei University of Technology,Hefei 230009,China
  • Received:2021-03-24 Online:2022-09-15 Published:2022-09-15
  • Supported by:
    National Natural Science Foundation of China(61874156);Collaborative Innovation Funding Project for Universities in Anhui(GXXT-2019-030)


The performance of microprocessors has been greatly improved by the development of heterogeneous multi-core technology. The bandwidth difference between the processor and external memory severely limits the performance of the processor, and the "Memory Wall" problem is becoming increasingly serious. For a heterogeneous multi-core SoC system in high-density computing, this study proposes a set of memory design scheme. The solution increases memory access bandwidth and reduces the frequency of accessing external memory by reusing some local free memory resources that have been idle for a long time as shared L2 cache. Meanwhile, the distributed high-speed shared L2 cache combined with the hierarchical storage structure of multi-channel parallel access to external storage alleviates the speed difference between system processing data and external storage, improves data access efficiency, and optimizes system performance. In terms of resource consumption and computing efficiency, the proposed design saves 69.36% of on-chip SRAM resources compared with ordinary L2 cache, provides 41.2% speedup ratio compared with non-cache structure, and reduces the overall task calculation time by about 40.6% on average.

Key words: heterogeneous multicore, memory wall, multiplexing, multiplexed parallelism, hierarchical memory, L2 cache, distributed, external memory

CLC Number: 

  • TN47