载波同步中数字锁相环的重构设计

doi:10.16180/j.cnki.issn1007-7820.2019.08.009

Abstract

Abstract:

Aiming at the problem that the development efficiency of the code or device in the previous carrier synchronous phase-locked loop is inherited and non-portable, a scheme of reconfiguring carrier synchronous PLLs in the form of reusing FPGA components was proposed. The scheme extracted the common modules of different phase-locked loops through functional decomposition, mapped suitable algorithms for functional modules and implemented them in FPGA. The method used the OCP protocol to encapsulate the interface to generate the FPGA component, and finally reused component to construct a new phase-locked loop application. The simulation results showed that the component reuse rate exceeded 60%, proving the correctness and effectiveness of the new method.

Key words: reconfiguration, digital PLL, carrier synchronous, component, OCP, FPGA

CLC Number:

TN876.4

DUAN Tie,HUANG Yan,WANG Yang. Reconfiguration Design of Digital PLL in Carrier Synchronous[J].Electronic Science and Technology, 2019, 32(8): 41-45.

Figures/Tables 8

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References 16

[1]	高瑞林 . 数字中频接收机载波同步技术研究[D]. 西安: 西安电子科技大学, 2014.
	Gao Ruilin . Research on the carrier synchronization technologies of digital IF receievers[D]. Xi’an: Xidian University, 2014.
[2]	尹伟 . 高阶QAM载波同步研究与实现[D]. 武汉:华中科技大学, 2013.
	Yin Wei . Reserch and implementation of carrier Synchronization for high-order QAM[D]. Wuhan: Huazhong University of Science and Technology, 2013.
[3]	周淳, 邓中亮 . 嵌入式组件技术的研究及应用[J]. 现代电子技术, 2009,32(6):50-52.
	Zhou Chun, Deng Zhongliang . Investigation and application of embedded component technology[J]. Modern Electronics Technique, 2009,32(6):50-52.
[4]	Hepard Siegel. Applying open standard to FPGA IP interfaces [C].Boston:MIT Lincoln Laboratory 11 ^th Annual Workshop on High Performance Embedded Computing , 2007.
[5]	沈宙, 马忠松 . 高速卫星通信中全数字载波同步算法的研究[J]. 国外电子测量技术, 2014,33(4):36-39.
	Shen Zhou, Ma Zhongsong . Study of high speed satellite digital carrier synchronization algorithm[J]. Foreign Electronic Measurement Technology, 2014,33(4):36-39.
[6]	王正磊, 周新力, 宋斌斌 . 一种基于改进平方环的解调方法的实现[J]. 电子设计工程, 2018,26(1):102-105.
	Wang Zhenglei, Zhou Xinli, Song Binbin . FPGA implementation of MSK demodulation based on modified squariong[J]. Electronic Design Engineering, 2018,26(1):102-105.
[7]	杜勇 . 数字通信同步技术的MATLAB与FPGA实现[M]. 北京: 电子工业出版社, 2013.
	Du Yong. Implementation of digital communication synchronization technology based on MATLAB and FPGA[M]. Beijing: Electronics Industry Press, 2015.
[8]	吕鑫宇, 姚远程, 潭清怡 , 等. 基于直接提取载波技术的平方环设计[J]. 现代电子技术, 2010,33(1):189-192.
	Lv Xinyu, Yao Yuancheng, Tan Qingyi , et al. Design of Squaring Loop Based on Direct Carrier Extraction[J]. Modern Electronics Technique, 2010,33(1):189-192.
[9]	焦淑红, 智扬 . 基于FPGA的高阶FIR滤波器设计[J]. 电子科技, 2015,28(8):24-28.
	Jiao Shuhong, Zhi Yang . Design of high order FIR filter design based on FPGA[J]. Electronic Science and Technology, 2015,28(8):24-28.
[10]	Neal Stollon,Bob Uvacek,Gilbert Laurenti. Standard debug interface socket requirments for OCP-ComPliant SoC[EB/OL].( 2007- 03- 12)[2018-05-06] .
[11]	IEEE. IEEE standard for IP-XACT,standard structure for packaging, integrating, and reusing IP within tool flows[M]. New York: The Institute of Electrical and Electronics Engineers,Inc, 2010.
[12]	Joint Program Executive Office . JTRS V3.1x,extension for component portability for specialized hardware processors (SHP) change proposal 289(CP289)[S]. CA:Joint Program Executive Office, 2005.
[13]	董胜 . 信号处理平台中 FPGA 的组件化运行环境的设计与实现[D]. 郑州:解放军信息工程大学信息, 2017.
	Dong Sheng . Design and implementation of FPGA componentize operating environment on signal processing platform[D]. Zhengzhou:PLA Information Engineering University, 2017.
[14]	袁泉 . 多模式解调技术的研究与实现[D]. 哈尔滨:哈尔滨工业大学, 2016.
	Yuan Quan . Research and realization of dynamic partial reconfigurable demodulation[D]. Harbin:Harbin Institute of Technology, 2016.
[15]	张平平 . DPSK解调系统的FPGA实现[D]. 西安:西安电子科技大学, 2015.
	Zhang Pingping . The FPGA implementation of DPSK demodulation system[D]. Xi’an:Xidian University, 2015.
[16]	杜勇 . 数字调制解调技术的MATLAB与FPGA实现[M]. 北京: 电子工业出版社, 2015.
	Du Yong. Implementation of digital modulation and demodulation technology based on MATLAB and FPGA[M]. Beijing: Electronics Industry Press, 2015.

功能模块	算法映射	实体化
乘法器	乘法	乘法器IP核
低通滤波器	FIR滤波器	FIR低通滤波器
低通滤波器	IIR滤波器	IIR低通滤波器
鉴相器	Costas鉴相器	符号判决、取反
	判决反馈环鉴相器	积分、抽样、符号判决
	平方环鉴相器	乘法器和低通滤波器
	DD锁相环	求门限值、符号判决、移位加法
环路滤波器	一阶环	仅实体化二阶环
	二阶环
	三阶环
NCO	查找表	DDS IP核
NCO	CORDIC算法	CORDIC IP核
平方变换	乘法	乘法器IP核
2分频模块	乘法	乘法器IP核
带通滤波器	IIR滤波器	IIR带通滤波器

编号	组件	位宽/bit		连接序号		组件参数
编号	组件	输入	输出	输入	输出	组件参数
1	鉴相器	32	32	4,5	3	——
2	DDS	32	8	3	6,7	频率字更新周期 R_F=8CLK
3	环路滤波器	32	32	1	2	系数:C₁=2^-5, C₂=2^-12
4	FIR低通滤波器1	16	32	6	1	系数:15,-22,-76, 129,511,511,129, -76,-22,15
5	FIR低通滤波器2	16	32	7	1	同上
6	乘法器1	8	16	2	4	——
7	乘法器2	8	16	2	5	——

锁相环	捕获时间/ms		测试信号	信号参数
锁相环	传统方式	重构方式	测试信号	码速率	采样率	载波	频偏
Costas环	0.60	0.61	BPSK	4 MHz	32 MHz	70 MHz	23.4 kHz
判决反馈环	0.33	0.42	QPSK	1 MHz	8 MHz	2 MHz	0.5 kHz
平方环	0.98	1.07	MSK	1 MHz	16 MHz	3 MHz	23.4 kHz
DD锁相环	12.50	13.23	QAM	1 MHz	8 MHz	2 MHz	1 kHz

组件	Costas环	判决反馈环	平方环	DD锁相环
乘法器	√	√	√	√
FIR低通滤波器	√	√		√
IIR低通滤波器			√
Costas鉴相器	√
判决反馈环鉴相器		√
DD鉴相器				√
环路滤波器	√	√	√	√
IIR带通滤波器			√
DDS组件	√	√	√
CORDIC 组件				√
复用率	——	80%	60%	60%

Reconfiguration Design of Digital PLL in Carrier Synchronous

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