[1] |
ZHANG Runyu, HE Yunlong, ZHENG Xuefeng, ZHANG Junjie, ZHOU Xiang, MA Xiaohua, HAO Yue.
GaN-based LLC resonant converter with a 2.5 MHz resonant frequency
[J]. Journal of Xidian University, 2024, 51(5): 1-8.
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[2] |
ZHANG Hangyu, ZHANG Rui, LIAO Fangyuan, LI Yongzhao.
Precoding scheme for massive MIMO with one-bit DACs based on cross entropy
[J]. Journal of Xidian University, 2022, 49(6): 1-8.
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[3] |
YU Jianhai,YIN Liang.
Design of an ADC with the submicron process for micromechanical accelerometers
[J]. Journal of Xidian University, 2019, 46(3): 140-147.
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[4] |
CHEN Zhenhai, WEI Jinghe, YU Zongguang, SU Xiaobo, XUE Yan, ZHANG Hong.
High precision common mode charge error fore-ground calibration circuit for the charge-domain ADC
[J]. Journal of Xidian University, 2018, 45(6): 137-143+149.
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[5] |
DING Hao;WANG Jianye;LIU Wei;XIONG Yongzhong.
High-speed high-broadband master-slave sampling and hold circuit
[J]. Journal of Xidian University, 2018, 45(4): 123-128.
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[6] |
ZHANG Zhang;YU Wencheng;XIE Guangjun.
10bit 100MS/s Hybrid ADC
[J]. Journal of Xidian University, 2018, 45(3): 80-85+116.
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[7] |
CHEN Zhenhai;WEI Jinghe;SU Xiaobo;ZOU Jiaxuan;ZHANG Hong;YU Zongguang.
Low power time-interleaved 12-bit 500MS/s charge-domain ADC
[J]. Journal of Xidian University, 2017, 44(6): 109-115+137.
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[8] |
CHEN Zhenhai;YU Zongguang;LI Xiankun;WEI Jinghe;HUANG Songren;SU Xiaobo.
High precision voltage reference generator for 16-bit 100MS/s ADC
[J]. Journal of Xidian University, 2017, 44(3): 127-132+180.
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[9] |
HUANG Songren;CHEN Zhenhai;ZHANG Hong;LI Xue;QIAN Hongwen;YU Zongguang.
1.5bit substage circuit for charge domain pipelined ADCs
[J]. Journal of Xidian University, 2016, 43(6): 170-175.
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[10] |
WANG Xiaofei;HAO Yue.
Design of double sample 1.2V 7bit 125MS/s pipelined ADC
[J]. Journal of Xidian University, 2016, 43(4): 23-28.
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[11] |
XIA Pu;LIU Xuebin;YAN Peng.
Design of and experiment on the polarization dehazing imaging system
[J]. Journal of Xidian University, 2016, 43(2): 95-101.
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[12] |
DONG Siwan;ZHU Zhangming;LIU Minjie;YANG Yintang.
Optimum design of the MDAC circuit for the 8bit 80MS/s pipelined A/D converter
[J]. J4, 2016, 43(1): 162-166+172.
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[13] |
CAO Chao;MA Rui;ZHU Zhangming;LIANG Yuhua;YE Qian.
Analysis of non-ideal factors and digital calibration for highresolution SAR ADCs
[J]. J4, 2015, 42(6): 61-65+87.
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[14] |
YANG Yintang;YUAN Jun;ZHANG Zhaofeng.
Continuous time ΣΔADC design with 256MHz sampling and 71dB DR
[J]. J4, 2015, 42(1): 10-15.
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[15] |
FANG Biao;HUANG Gaoming;GAO Jun;ZUO Wei.
Design of a segmented and blocked compressive sampling model
[J]. J4, 2014, 41(4): 151-157.
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