Abstract:

In order to reduce the pin count, the cost and size of packaging, and complexity of system design, a high speed serial interface protocol named JESD204B has been proposed by the JEDEC committee. This paper presents a specific implementation scheme of the transceiver controller based on this protocol. The implemented controller of the transceiver with 4 lanes has been verified with the high speed serial transceiver Xilinx FPGA GTH under a data rate of 6.25Gbit/s.

Key words: implementation of JESD204B, high speed serial data transmission, field programmable gata array, converter, design of data acquisition system