基于FPGA的高效并行HDMI 2.0编码器设计

doi:10.16180/j.cnki.issn1007-7820.2021.04.006

Abstract

Abstract:

An efficient parallel HDMI 2.0 encoder is designed to solve the problems of poor scalability and large circuit area in the design of multi-channel video display system. The compatibility of HDMI 2.0 encoder has been improved through the compatibility design of HDMI version 1.4 and 2.0 standards. The scalability and portability of HDMI 2.0 encoder are improved by simplifying functions and providing user-friendly data interfaces. Through parallel design, the ECC circuit and the scramble circuit are kept at the same data rate as the entire encoder, and a pipelined design method was used to implement the parallel encoding of the video data encoding circuit. The result analysis, function simulation and on-board test are carried out and their results show that the HDMI 2.0 encoder conforms to the HDMI standard and can stably perform encoding and output. The results also showed that the coding ability of ultra-HD video is possessed by HDMI 2.0 encoder designed in parallel, which can reach the maximum coding bandwidth of HDMI 2.0 standard.

Key words: multi-channel video, HDMI, encoder, parallel design, ECC, scrambling, pipeline, ultra-HD video

CLC Number:

TN919.8

GONG Jialiang,TANG Qingshan,BAI Chuang. Design of Efficiency Parallel HDMI 2.0 Encoder Based on FPGA[J].Electronic Science and Technology, 2021, 34(4): 34-40.

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References 18

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加扰因子输出序号	数据通道 0加扰因子值	加扰因子输出序号	数据通道 0加扰因子值	加扰因子输出序号	数据通道 0加扰因子值
种子值	FFFF	11	14B3	22	5547
1	77EB	12	9B17	23	3F59
2	4B7C	13	BF87	24	693A
3	A445	14	67A4	25	3A60
4	DDBD	15	CC6F	26	883F
5	EDCE	16	CFDC	27	1797
6	FEFA	17	34DF	28	F714
7	4AEA	18	5F30	29	64E2
8	0A44	19	C052	30	C26C
9	CC0B	20	EAD1	31	A4D3
10	ABDC	21	49FD

	串行	两字符并行	四字符并行
最大时钟频率/MHz	457.9	457.9	461.7
寄存器数/个	753	1 253	2 281

Design of Efficiency Parallel HDMI 2.0 Encoder Based on FPGA

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