Electronic Science and Technology ›› 2021, Vol. 34 ›› Issue (4): 34-40.doi: 10.16180/j.cnki.issn1007-7820.2021.04.006

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Design of Efficiency Parallel HDMI 2.0 Encoder Based on FPGA

GONG Jialiang,TANG Qingshan,BAI Chuang   

  1. School of Physics and Electronic Science,Changsha University of Science and Technology,Changsha 410114,China
  • Received:2020-01-02 Online:2021-04-15 Published:2021-04-16
  • Supported by:
    Excellent Youth Project of Hunan Provincial Department of Education(18B164);Changsha Science and Technology Bureau(KQ1901099)


An efficient parallel HDMI 2.0 encoder is designed to solve the problems of poor scalability and large circuit area in the design of multi-channel video display system. The compatibility of HDMI 2.0 encoder has been improved through the compatibility design of HDMI version 1.4 and 2.0 standards. The scalability and portability of HDMI 2.0 encoder are improved by simplifying functions and providing user-friendly data interfaces. Through parallel design, the ECC circuit and the scramble circuit are kept at the same data rate as the entire encoder, and a pipelined design method was used to implement the parallel encoding of the video data encoding circuit. The result analysis, function simulation and on-board test are carried out and their results show that the HDMI 2.0 encoder conforms to the HDMI standard and can stably perform encoding and output. The results also showed that the coding ability of ultra-HD video is possessed by HDMI 2.0 encoder designed in parallel, which can reach the maximum coding bandwidth of HDMI 2.0 standard.

Key words: multi-channel video, HDMI, encoder, parallel design, ECC, scrambling, pipeline, ultra-HD video

CLC Number: 

  • TN919.8