Journal of Xidian University ›› 2022, Vol. 49 ›› Issue (6): 58-66.doi: 10.19665/j.issn1001-2400.2022.06.008
• Information and Communications Engineering • Previous Articles Next Articles
WANG Pengjun1(),CHEN Jia2(),ZHANG Yuejun2(),ZHUANG Youyi1(),LI Lewei2(),NI Li2()
Received:
2021-12-30
Online:
2022-12-20
Published:
2023-02-09
CLC Number:
WANG Pengjun,CHEN Jia,ZHANG Yuejun,ZHUANG Youyi,LI Lewei,NI Li. Software PUF with multiple entropy sources based on path sensitization[J].Journal of Xidian University, 2022, 49(6): 58-66.
[1] |
ALRAHIS L, SENGUPTA A, KNECHTEL J, et al. GNN-RE:Graph Neural Networksfor Reverse Engineering of Gate-Level Netlists[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 41(8):2435-2448.
doi: 10.1109/TCAD.2021.3110807 |
[2] |
ALRAHIS L, PATNAIK S, KNECHTEL J, et al. UNSAIL:Thwarting Oracle-Less Machine Learning Attacks on Logic Locking[J]. IEEE Transactions on Information Forensics and Security, 2021, 16:2508-2523.
doi: 10.1109/TIFS.2021.3057576 |
[3] | POKORNY D, SOCHA P, NOVOTNY M. Side-Channel Attack on Rainbow Post-Quantum Signature[C]// Proceedings of the 2021 Design,Automation & Test in Europe Conference & Exhibition (DATE).Piscataway:IEEE, 2021:565-568. |
[4] | 赵毅强, 曹宇文, 何家骥, 等. 抗电磁侧信道攻击随机预混淆逻辑单元设计[J]. 西安电子科技大学学报, 2022, 49(4):167-175. |
ZHAO Yiqiang, CAO Yuwen, HE Jiaji, et al. Design of Random Pre-Obfuscation Logic Units Against EM Side-Channel Attack[J]. Journal of Xidian University, 2022, 49(4):167-175. | |
[5] |
ZHANG J, LIN Y, LYU Y. A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-per-Device Licensing[J]. IEEE Transactions on Information Forensics and Security, 2015, 10(6):1137-1150.
doi: 10.1109/TIFS.2015.2400413 |
[6] |
LIN L, SRIVATHSA S, KRISHNAPPA D K, et al. Design and Validation of Arbiter-Based PUFs for Sub-45-nm Low-Power Security Applications[J]. IEEE Transactions on Information Forensics and Security, 2012, 7(4):1394-1403.
doi: 10.1109/TIFS.2012.2195174 |
[7] |
ZALIVAKA S S, IVANIUK A A, CHANG C. Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation with Trinary Quadruple Response[J]. IEEE Transactions on Information Forensics and Security, 2019, 14(4):1109-1123.
doi: 10.1109/TIFS.2018.2870835 |
[8] | MAITI A, SCHAUMONT P. Improving the Quality of a Physical Unclonable Function Using Configurable Ring Oscillators[C]// Proceedings of the 2009 International Conference on Field Programmable Logic and Applications.Piscataway:IEEE, 2009:703-707. |
[9] |
ALVAREZ A B, ZHAO W, ALIOTO M. Static Physically Unclonable Functions for Secure Chip Identification with 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm[J]. IEEE Journal of Solid-State Circuits, 2016, 51(3):763-775.
doi: 10.1109/JSSC.2015.2506641 |
[10] |
ZHANG Y, PAN Z, WANG P, et al. A 0.1-pJ/b and ACF<0.04 Multiple-Valued PUF for Chip Identification Using Bit-line Sharing Strategy in 65 nm CMOS[J]. IEEE Transactions on Very Large Scale Integration Systems, 2019, 27(5):1043-1052.
doi: 10.1109/TVLSI.2019.2896142 |
[11] | NGUYEN P H, SAHOO D P, JIN C, et al. The Interpose PUF:Secure PUF Design Against State-of-the-Art Machine Learning Attacks[J]. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2019, 2019(4):243-290. |
[12] | HE Z, CHEN W, ZHANG L, et al. A Highly Reliable Arbiter PUF with Improved Uniqueness in FPGA Implementation Using Bit-Self-Test[J]. IEEE Access, 2020, 8:181751-181762. |
[13] | RAHMAN M T, RAHMAN F, FORTE D, et al. An Aging-Resistant RO-PUF for Reliable Key Generation[J]. IEEE Transactions on Emerging Topics in Computing, 2016, 4(3):335-348. |
[14] | DENG D, HOU S, WANG Z, et al. Configurable Ring Oscillator PUF Using Hybrid Logic Gates[J]. IEEE Access, 2020, 8:161427-161437. |
[15] | SHIFMAN Y, MILLER A, KEREN O, et al. A Method to Improve Reliability in a 65-nm SRAM PUF Array[J]. IEEE Solid-State Circuits Letters, 2018, 1(6):138-141. |
[16] |
ZHENG Y, ZHANG F, BHUNIA S. DScanPUF:A Delay-Based Physical Unclonable Function Built into Scan Chain[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(3):1059-1070.
doi: 10.1109/TVLSI.2015.2421933 |
[17] | WANG S J, LIEN C H, LI K S M. Register PUF with No Power-up Restrictions[C]// Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS).Piscataway:IEEE, 2018:1-5. |
[18] | MAITI A, SCHAUMONT P. A Novel Microprocessor-Intrinsic Physical Unclonable Function[C]// Proceedings of the International Conference on Field Programmable Logic & Applications.Piscataway:IEEE, 2012:380-387. |
[19] |
AYSU A, SCHAUMONT P. Hardware/Software Co-design of Physical Unclonable Function Based Authentications on FPGAs[J]. Microprocessors and Microsystems, 2015, 39(7):589-597.
doi: 10.1016/j.micpro.2015.04.001 |
[20] | CHEN J, WANG P, ZHANG Y, et al. SPUF Design Based on Camellia Encryption Algorithm[J]. Microelectronics Journal, 2021, 112:105051. |
[21] | BUSHNELL M L, AGRAWAL V D. 超大规模集成电路测试——数字、存储器和混合信号系统[M]. 北京: 电子工业出版社, 2005:117-118. |
[22] |
LI G, WANG P, MA X, et al. A Multimode Configurable Physically Unclonable Function with Bit-Instability-Screening and Power-Gating Strategies[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 29(1):100-111.
doi: 10.1109/TVLSI.2020.3030945 |
[23] |
LI G, WANG P, ZHANG Y, et al. A Multi-port Low-power Current Mode PUF Using MOSFET Current-Division Deviation in 65 nm Technology[J]. Microelectronics Journal, 2017, 67:169-175.
doi: 10.1016/j.mejo.2017.07.017 |
[24] | WISIOL N. Towards Attack Resilient Arbiter PUF-Based Strong PUFs[J/OL].[2022-2-5]. https://eprint.iacr.org/2021/1004.pdf. |
[25] | WISIOL N, MURSI K T, SEIFERT J P, et al. Neural-Network-Based Modeling Attacks on XOR Arbiter PUFs Revisited[J/OL].[2022-2-9]. https://eprint.iacr.org/2021/555.pdf. |
[1] | LI Lin,ZHANG Huihong,ZHANG Yuejun. Design of the line calculation circuit based on capacitive coupling of interconnection lines [J]. Journal of Xidian University, 2022, 49(3): 213-221. |
[2] | NGUYEN Van-Truong,CAI Jueping,WEI Linyu,CHU Jie. Low complexity probability-based piecewise linear approximation of the sigmoid function [J]. Journal of Xidian University, 2020, 47(3): 58-65. |
[3] | WU Qiufeng,ZHANG Yuejun,WANG Pengjun,ZHANG Huihong. Hardware obfuscation design of the RM logical camouflage gate [J]. Journal of Xidian University, 2020, 47(2): 135-141. |
[4] | ZHANG Yan;YANG Yintang. Novel distributed optimal interconnection power model [J]. J4, 2014, 41(4): 36-40+192. |
[5] | LIU Maliang;ZHU Zhangming;GUO Xulong;YANG Yintang. 4-channel-interpolated 14-bit high speed CORDIC DDS IP core [J]. J4, 2013, 40(6): 62-66. |
[6] | YUAN Bo;LIU Hongxia. Optimization methodology for the width of the fixed-point decimal multiplier [J]. J4, 2013, 40(5): 113-118. |
[7] | YUAN Bo;LIU Hongxia. Optimization methodology for the number of additions in multiplier [J]. J4, 2013, 40(3): 102-108. |
[8] | LIU Yi;CHEN Bo;YANG Yintang;LIU Gang. High-speed low-power clock network design for NoC [J]. J4, 2013, 40(3): 115-120. |
[9] | LI Xiaojuan;YANG Yintang. Offset cancellation preamplifier for pipelined folding A/D converter [J]. J4, 2012, 39(2): 95-100+174. |
[10] | YANG Yanfei;ZHU Zhangming;ZHOU Duan;YANG Yintang. Delay-independent asynchronous dynamic priority arbiter for the network on chips [J]. J4, 2012, 39(1): 42-48+110. |
[11] | LIU Lianxi;YANG Yintang;ZHU Zhangming. Design of a high output power step down DC/DC converter with the peak current control mode [J]. J4, 2011, 38(2): 135-140. |
[12] |
LIU Lian-xi;YANG Yin-tang;ZHU Zhang-ming.
Design of a high efficiency and filterless stereo class-D audio power amplifier [J]. J4, 2009, 36(2): 308-313. |
[13] |
SHAN Guang-bao1;YANG Yin-tang2;LIU You-bao1;ZHU Zhang-ming2.
Modeling of the micro-silicon gyroscope [J]. J4, 2007, 34(2): 227-232. |
[14] |
YANG Yin-tang;REN Le-ning;FU Jun-xing.
Ultra-low voltage operational amplifier based on quasi-floating gate transistors |
[15] |
LIU Lian-xi;YANG Yin-tang;ZHU Zhang-ming.
A low voltage and high accuracy CMOS bandgap reference by considering mismatch of MOSFETs [J]. J4, 2005, 32(3): 348-352. |
|