Abstract:

The RLWE encryption scheme is one of the most potential candidates in the lattice cryptosystem in the post-quantum era. In view of the problem of high latency and low throughput in RLWE cryptoprocessor, this study proposes a high-performance RLWE cryptoprocessor hardware architecture. The parallel circuit structure of two NTT modules and four butterfly modules are adopted in the proposed architecture. In the pre-calculation and post-calculation process, the multipliers in the four butterfly modules are used for parallel calculation. In the encryption process, NTT calculation and ciphertext calculation are performed in parallel. In the processing of NTT and INTT operations, the data read and write process and calculation process are ping-pong operations, thereby hiding the data read and write cycle, reducing the delay of the RLWE encryption processor, and improving the throughput of the RLWE encryption processor. A hardware architecture is designed for resource reuse, the multiplier and adder are reused in the butterfly module during the encryption and decryption process, and the circuit structure of NTT is reused by INTT, thereby reducing the hardware resource consumption of the encryption processor. The cryptoprocessor with parameters of n=256 and q=65 537 is implemented on the Spartan-6 FPGA development platform. The results indicate that the encryption time is only 12.18 μs, the throughput is 21.01 Mbit·s^-1, the decryption time is only 8.65 μs, and the throughput is 29.60 Mbit·s^-1. Compared with other cryptoprocessor, the proposed design has improved the delay and throughput of the cryptoprocessor.

Key words: post-quantum, FPGA, ring learning with error, encryption, throughput, latency, parallel, resource reuse